1. Field of the Invention
The present invention relates to a semiconductor device package, and more particularly, to a semiconductor device package including a plurality of semiconductor memory devices.
2. Description of Related Art
Much time and effort has been spent developing higher capacity semiconductor memory devices. Accordingly, memory manufacturers have increased the capacity of semiconductor memory devices using double die package DDP technology in which two semiconductor chips are stacked upon one another in a single package. Stacked package technology has also been developed in which two semiconductor packages are stacked upon one another in a single package.
For example, a semiconductor memory device with a memory capacity of 512 Mbits of data can be manufactured using two semiconductor memory chips or packages each having a memory capacity of 256 Mbits. Another example is a semiconductor memory device with a 1 Gbit memory capacity comprising two semiconductor chips or packages each having 512 Mbits of memory capacity.
FIG. 1 illustrates an external pin configuration of a conventional semiconductor memory device with 512 Mbits of memory capacity. The external pins of the conventional semiconductor device 100 include a power voltage pin VDD, a ground voltage pin VSS, address pins A1˜A12, band address pins BA0 and BA1, command pins CSB, WEB, CASB and RASB, and data input/output pins DA0˜DQ3.
The semiconductor memory device 100 shown in FIG. 1 includes four memory cell array banks, each of which includes an array of 213 rows by 212 columns of memory cells. Each cell is accessed according to address signals including 13 row address bits (RA0˜RA12) and 12 column address bits (CA0˜CA12). Each memory cell is capable of processing four data bits, which are input or output via four data input/output ports. Thus, the semiconductor memory device 100 has a total memory capacity becomes 213×212×4×4=512 Mbits.
The operation of the semiconductor memory device 100 shown in FIG. 1 to perform a read/write data operation will be described below.
Operation of the semiconductor memory device 100 is enabled in response to receiving a set of signals, including an inverted chip selective signal applied to the inverted chip selective signal pin CSB, an inverted row address strobe command applied to the inverted row address strobe pin RASB, 13 row address bit signals (RA0˜RA12) applied to the address pins A0˜A12, and the bank address signals applied to the bank address pins BA0 and BA1.
Another set of signals is then applied to the semiconductor memory device 100 to perform the read/write operation. These signals include an inverted column address strobe command applied to the inverted column strobe pin CASB, 12 column address bit signals (CA0˜CA9, CA11 and CA12) along with a one bit auto precharge command (CA10) applied to address pins A1˜A12, and an inverted write enable signal applied to the inverted write enable signal pin WEB.
Consequently, 4 bits of data are input to the device 100 through the data input/output pins DQ0˜DQ3 if a write operation is being performed. Alternatively, 4 bits of data are output from the data input/output pins DQ0˜DQ3 if a read operation is being performed.
FIG. 2 illustrates an external pin configuration of a semiconductor memory device package 200 having a 1 Gbit memory capacity, which incorporates two of the 512 Mbit capacity semiconductor memory devices 100 of FIG. 1. The external pin configuration of the semiconductor memory device package includes a power voltage pin VDD, a ground voltage pin VSS, address input pins A0˜A12, bank address input pins BA0˜BA1, command input pins CSB1, CSB2, WEB, CASB and RASB, and data input/output pins DQ1˜DQ3.
The external pin configuration of the semiconductor memory device package 200 shown in FIG. 2 includes two inverted chip selective signal pins CSB1 and CSB2, rather than the one inverted chip selective signal pin CSB of the semiconductor memory device 100 shown in FIG. 1. During a read/write data operation, the semiconductor memory device package 200 receives an inverted chip selective signal in one of the pins CSB1 and CSB2 to determine which of the two 512 Mbit semiconductor chips is to perform the data operation.
FIG. 3 illustrates connections between memory chip pads of the conventional 512 Mbit capacity semiconductor memory devices 100 and the external pins of the conventional 1 Gbit semiconductor memory device package. Specifically, FIG. 3 illustrates the 512 Mbit capacity chips implemented in the semiconductor package 200 as an upper memory chip 10-1 and a lower memory chip 10-2.
Referring to FIG. 3, each of the upper and lower memory chips 10-1 and 10-2 include a power voltage pad PVDD; a ground voltage pad PVSS; an address pad including address input terminals PA1˜PA12; a bank address pad including bank address input terminals PBA0 and PBA1; a command pad including command input terminals PCSB, PWEB, PCASB, and PRASB; and a data input/output pad including data input/output terminals PDQ0˜PDQ3.
Also, FIG. 3 shows the external pins to which the corresponding chip pads and terminals of the upper and lower memory chips 10-1 and 10-2 are commonly connected. The external pins include a power voltage pin VDD; a ground voltage pin VSS; address input pins A0˜A12; bank address input pins BA0 and BA1; command input pins CSB1, CSB2, WEB, CASB and RASB; and data input/output pins DQ0˜DQ3.
Referring to FIG. 3, all of the pads and terminals of each of the upper and the lower memory chips 10-1 and 10-2 are commonly connected to the corresponding external pins with the exception of the respective inverted chip selective signal input terminals PCSB. The inverted chip selective signal input terminal PCSB of the upper memory chip 10-1 is connected to the external inverted chip selective signal pin CSB1, and the inverted chip selective signal input terminal PCSB of the lower memory chip 10-2 is connected to the external inverted chip selective signal pin CSB2.
In other words, the conventional semiconductor memory device package 200 shown in FIG. 2 and FIG. 3 is configured such that the upper memory chip 10-1 is enabled to perform a read/write data operation when an inverted chip selective signal is applied to the inverted chip selective signal pin CSB1, and enable the lower memory chip 10-2 to perform a data operation in response to an inverted chip selective signal applied to the inverted chip selective signal pin CSB2.
A read/write data operation is performed using the conventional semiconductor memory device package 200 shown in FIG. 2 and FIG. 3 will operate as follows.
When an inverted chip selective signal is applied to the inverted chip selective signal pad CSB1, and the other address, bank address and command input signals are applied to the read/write operation of the 512 Mbit device 100 of FIG. 1, the upper memory chip 10-1 performs the write/read operations to input/output data.
When an inverted chip selective signal is applied to the inverted chip selective signal pad CSB2, along with the other address, bank address and command input signals described above in connection with the read/write operation of the 512 Mbit device 100 of FIG. 1, the lower memory chip 10-2 performs the write/read operations to input/output data.
Thus, by incorporating two 512 Mbit capacity semiconductor memory chips or packages together into a single semiconductor package 200, a semiconductor memory device having a memory capacity of 1 Gbit can be manufactured.
However, the semiconductor memory device shown in FIGS. 2 and 3 is not capable of using a conventional semiconductor memory board layout, since the internal upper and lower memory chips 10-1 and 10-2 are separately enabled by chip selective signals applied to separate external pins (CSB1 and CSB2) of the semiconductor memory device package 200.
In other words, the conventional board is configured to control the semiconductor memory device using one chip selective signal rather than two. Accordingly, a board having a different type of configuration than the conventional board must be fabricated to utilize the semiconductor memory device package 200 shown in FIGS. 2 and 3.
FIG. 4 shows an external pin configuration of an alternative 1 Gbit capacity semiconductor memory device package in the conventional art, which incorporates two conventional 512 Mbit capacity semiconductor memory devices. The pin configuration shown in FIG. 4 differs with the pin configuration of the conventional semiconductor memory device package shown in FIG. 2 by including an additional address pin A13.
The 512 Mbit capacity memory chips used in the semiconductor memory device package 300 of FIG. 4 are different from the memory chip of FIG. 1 and include four memory cell array banks, where each memory cell array being arranged in 214 rows by 212 columns of cells. Thus, the memory cells are accessed using 14 row address bits (RA0˜RA13), 12 column address bits (CA0˜CA11). Each cell is capable of holding two bits of data, which are input or output via two data input/output ports. Accordingly, the total memory capacity becomes 214×212×4×2=512 Mbits. Since the semiconductor memory device package 300 incorporates two of these 512 Mbit capacity memory chips, the memory capacity of the semiconductor package 300 is 1 Gbit.
FIG. 5 illustrates connections between memory chip pads of the conventional 512 Mbit capacity memory chips and the plurality of external pins of the semiconductor package 300 of FIG. 4. FIG. 5 shows the 512 Mbit capacity chips implemented in the semiconductor package 300 as an upper memory chip 20-1 and a lower memory chip 20-2.
Referring to FIG. 5, each of the upper and lower memory chips 20-1 and 20-2 include a power voltage pad PVDD; a ground voltage pad PVSS; an address pad including address input terminals PA1˜PA13; a bank address pad including bank address input terminals PBA0 and PBA1; and a command pad including command input terminals PCSB, PWEB, PCASB and PRASB; and a data input/output pad including data input/output terminals PDQ0 and PDQ1.
Also, FIG. 5 shows the external pins to which the corresponding chip pads and terminals of the upper and lower memory chips 20-1 and 20-2 are connected. These external pins include a power voltage pin VDD; a ground voltage pin VSS; address input pins A0˜A13; bank address pins BA0 and BA1; command input pins CSB1, CSB2, WEB, CASB and RASB; and data input/output pins DQ0˜DQ3.
Referring to FIG. 5, all of the pads and terminals of each of the upper and the lower memory chips 20-1 and 20-2 are commonly connected to the corresponding external pins with the exception of the data input/output terminals PDQ0 and PDQ1. The data input/output pads PDQ0 and PDQ1 of the upper memory chip 20-1 is connected to the external data input/output pins DQ0 and DQ1, and the data input/output pads PDQ0 and PDQ1 of the lower memory chip 20-2 are connected to the external data input/output pins DQ2 and DQ3.
In other words, the conventional semiconductor memory device package 300 shown in FIG. 4 and FIG. 5 are configured to enable both the upper and the lower memory chip 20-1 and 20-2 to respond to an inverted chip selective signal applied to the inverted chip selective signal pin CSB and input or output data via their respective data input/output terminals PDQ0 and PDQ1. Thus, both memory chips 20-1 and 20-2 perform a read/write operation using their respective memory cell, which corresponds to the address bit signals applied to external pins A0˜A13. That is, the data is input or output through the external data input/output pins DQ0˜DQ3, the data bits at pins DQ0 and DQ1 being processed by the upper memory chip 20-1 and the data bits at DQ2 and D03 being processed by the lower memory chip 20-2.
However, while the conventional semiconductor memory device package 300 shown in FIG. 4 and FIG. 5 utilizes the conventional board layout, it dissipates a high amount of current because both the upper and lower memory chips 20-1 and 20-2 are configured to respond to the inverted chip selective signal CSB, thereby causing both chips 20-1 and 20-2 to simultaneously operate in order to perform a read/write data operation on either.